CPU design
The CPU was based on an invented instruction set architecture and took advantage of the Harvard Architecture philosophy, while building off the work done with ARMish in term two. The primary objective was to build a CPU that could do the benchmarks (Calculating Fibonacci numbers, pseudo-random integers with a linear congruential generator and traverse a linked list), while remaining general (Turing complete). Hence research on different ISAs like AVR, MIPS, SPARC, and ARM, as well as the Harvard Architecture was conducted. Some instructions were specifically developed for the benchmarks like multiply, subroutines, and stacks. After deciding upon a 12 instruction ISA to meet the benchmark requirements, the separate hardware blocks were decided. The CPU’s hardware took inspiration from the ARMish CPU built in term two, as it had a register file and ALU to carry out calculations. After implementing all instructions with hardware, the CPU was optimised to maximise power, speed, and area. This was done through pipelining, parallel computation, and analysis of different multipliers
There are several ways for the CPU to improve and to investigate further if there was more time. Firstly, in terms of the memory blocks, a dual port RAM could be tested, as this would probably be very similar to the current setup, while also being more compact. To make the CPU more general, a signed multiplier could be implemented with slightly more hardware to multiply signed numbers. More complex implementations of a multiplier could also be investigated to attempt to decrease the number of cycles it takes. Different implementations of the Fibonacci benchmark could also be tested, as the results showed that recursion is very inefficient execution time scales exponentially with the input parameter. An assembler for the invented ISA could also be made to make it easier to convert from assembly to machine code.